Low-power integrated circuits are desirable in most applications, and particularly in the field of mobile technology where power consumption is critical to the successful operation of the mobile device. Minimizing power in an integrated circuit typically starts at the gate level in any technology, but in CMOS technology in particular, some common techniques for power reduction are known in the art.
Leakage dissipation, short-circuit dissipation and dynamic dissipation in CMOS circuitry combine to form the total power dissipation of the integrated circuit. Leakage dissipation arises from substrate injection and sub-threshold effects and is primarily determined by the fabrication technology of the transistor. Dynamic or switching power consumption of a CMOS inverter arises when the capacitive load (CL) is charged through the PMOS transistor to make a voltage transition from zero to the high voltage level, which is usually the supply, Vdd. As such, the energy drawn from the power supply for this positive going transition is CLVdd2, half of which is stored in the output capacitor and half is dissipated in the PMOS device. Conversely, when the output switches from Vdd to zero, no charge is drawn from the supply, but the energy stored in the output capacitor is dissipated in the pull-down NMOS transistor. In the case of an inverter, short-circuit power dissipation arises when a PMOS and an NMOS transistor are simultaneously active, conducting current directly from the supply to ground. While this is unavoidable in CMOS gates due to the inability to instantaneously switch the gates, in sufficiently quickly switched gates, the fraction of short-circuit power is small in comparison to the dynamic power in most cases.
A prototypical integrated circuit includes pull-up circuitry and pull-down circuitry, as is commonly known as an inverter circuit, a capacitive load, CL, a high voltage node, Vdd, and a low voltage node, Vss. In this configuration, the energy drawn from the power supply for a positive going transition of the output node from a zero, to a one, is CLVdd2, half of which is stored in the output capacitor and half of which is dissipated in the pull-up circuitry. Conversely, when the output switches from Vdd to zero, no charge is drawn from the supply, but the energy stored in the output capacitor is dissipated in the pull-down circuitry. During this process of switching between a zero and a one, there is a fraction of time in which both the pull-up and the pull-down circuitry are simultaneously active. This results in a short-circuit situation from Vdd to Vss. As such, a current flow results in a dissipation of charge in the inverter.
Since the leakage dissipation is inherent in the design of the components themselves and weakly tied to the operating voltage, integrated circuit designers have little control over the static leakage of the circuit. Accordingly, power reduction techniques are commonly focused on minimizing the short-circuit and dynamic power dissipation of the integrated circuit. Low-power integrated circuit designs are commonly focused on either designing low-power circuitry or efficient power management. Low-power designs seek to reduce the power dissipation by lowering the operating voltages or the switching frequency thereby reducing the overall dynamic power of the device. However, lower operating voltages and slower frequencies also result in slower operating speeds. Efficient power management techniques strive to reduce the dynamic power dissipation in the integrated circuit through the optimization of the physical, circuit and logic levels. Some common techniques for efficient power management include optimizing placement of devices and routes of signals, transistor sizing, reducing swing logic, logic minimization and logic level power down. The techniques known in the art for efficient power management rely on architecture or algorithm level optimization of the integrated circuit to realize a reduction in power dissipation.
Power dissipation in an integrated circuit is a measure of the efficiency of the system. The efficiency of the system affects the design of the power supply for the system. Accordingly, systems that are inefficient waste more energy and therefore require a larger power supply. In battery-operated systems, such as mobile devices, the power dissipation in the system reduces the life of the battery. The more power dissipated, the larger the battery required to operate the device. Larger batteries requirements inherently increase the cost and weight of the system, which is undesirable in mobile devices. In addition to the wasted energy generated by an inefficient system, power dissipation generates heat. An inefficient system must therefore accommodate the increased heat dissipation in the system by utilizing heat sinks to protect the circuitry. Such heat sinks also add undesirable cost, size and weight to the mobile system.
While the techniques known in the art for reducing the power dissipation of integrated circuits have achieved, noted success, there exists an ongoing need in the art for additional systems and methods for minimizing the power dissipated by a digital system.